BUS INTERFACE UNIT (BIU):
1. The bus interface unit contains the circuit for physical address calculation and pre decoding instruction byte queue.
2. The BIU makes the system bus signal available for external interfacing of the device.
3. The unit is responsible for establishing communication with external device and peripherals are including memory via the bus.
4. The complete physical address from contents which is 20bits long is generated using segment and offset register. 5. For a generation of physical address from contents of these two registers the content of a segment register also called as segment address is shifted left bit wise 4-times and to this result, content of an offset register also called an offset address is added to produce a 20 bit physical address.
6. The bus interface unit has a separate address to perform this procedure for obtaining a physical address while addressing mode the segment address values is to be taken from an appropriate segment register depending upon the offset may be the content of IP, BX,SI,DI,SP,BP or an intermediate 16 bit values depending upon addressing mode.
7. In case of 8085 once operational code is fetched and decoded the external bus remain free for same time while the processor internally executes. While the fetched instruction is executed internally, the external bus is used to fetch the machine code of the next instruction and arrange it I a queue known as “PREDECODED INSTRUCTION BYTE QUEUE”.
8. The operational code is fetching by BIU and EU executes the previously decode instruction concurrently. The BIU along with the EU perform a pipe line.
9. The BIU thus manages the complete interface execution unit with memory and input and output decides under the control of timing and control unit.
