The circuit resemble AND gate. The boolean expression of this circuit is, `V_(0) = A.B " i.e., " V_(0)` equals A AND B. The truth table of this gate is as given below
`{:(ul(A" "B" "V_(0) = A.B)),(0" "0" "0),(0" "1" "0),(1" "0" "0),(ul(1" "1" "1)):}`
