Question

A 4-bit synchronous counter has flip-flops having propagation delay of 50 ns each and AND gates having propagation delay of 20 ns each. The maximum frequency of clock pulses can be
1. 20 MHz
2. 50 MHz
3. 14.3 MHz
4. 5 MHz

Answer 1

Correct Answer - Option 3 : 14.3 MHz

Concept:

For a n-bit synchronous counter,

Tclk ≥ tff + tAND

Where, tff – propagation delay of flip flop

tAND – propagation delay of AND gate

Calculation:

Number of bits of a synchronous counter (n) = 4

The propagation delay of flip flop = 50 ns

The propagation delay of AND gate = 20 ns

Tclk ≥ 50 + 20

⇒ Tclk ≥ 70 ns

The minimum time interval required between two successive clock pulses for reliable operation of the counter is 50 ns.

The maximum frequency of clock pulses \( = \frac{1}{{70 \times {{10}^{ - 9}}}} = 14.28\;MHz\)