Correct option is (4)
Gate I, II and III are NOR gates and gate IV is NAND gate. Using the truth tables of gate involved we have

In Fig. the gates have been numbered as I, II, III and IV. Their outputs are labled as Y1 , Y2 , Y3 and Y respcetively. Using the Truth–table of NAND gate we have

In terms A, B and Y the correct Truth–table is given in (1).